Temperature aware microprocessor floorplanning considering application dependent power load

This paper studies microprocessor floorplanning considering thermal and throughput optimization. We first develop a stochastic heat diffusion model taking into account the application dependent power load for thermal analysis. Then, we design the floorplanning algorithm based on this model. Experimental results show that, compared with the deterministic heat diffusion model, our model obtains up to 3.2degC reduction of the on-chip peak temperature, 1.25% reduction of the area, and 1.125times better CPI (cycles per instruction) performance, respectively. Compared with temperature aware floorplanning in the HOTSPOT tool set that ignores interconnect pipelining, our algorithm is up to 27times faster, reduces the peak temperature by up to 3degC, and also reduces CPI significantly with a negligible area overhead.