Principle Hessian Direction based parameter reduction with process variation

As CMOS technology enters the nanometer regime, the increasing process variation is bringing manifest impact on circuit performance. In this paper, we propose a principle Hessian direction (PHD) based parameter reduction approach. This new approach relies on the impact of each parameter on circuit performance to decide whether keeping or reducing the parameter. Compared with the existing principle component analysis (PCA) method, this performance based property provides us a significantly smaller set of parameters after reduction. The experimental results also support our conclusions. In all cases, an average of 53% of reduction is observed with less than 3% error in the mean value and less than 8% error in the variation.