Yield-driven near-threshold SRAM design

Voltage scaling is desirable in SRAM to reduce energy consumption. However, commercial SRAM is prone to functional failures when V_dd is scaled. Several SRAM designs scale V_dd to 200-300 mV to minimize energy per access, but these designs do not consider SRAM robustness, limiting them to small arrays and sensor type applications. We examine the effects on area and energy for a differential 6 T, single-ended 6 T with power rail collapsing and an 8 T bitcell as V_dd is scaled and the bitcells are sized appropriately to maintain robustness. SRAM robustness is examined using importance sampling to reduce simulation runtime. At high voltages, the differential 6T bitcell is the smallest for the same failure rate, but the 8 T bitcell is smaller when V_dd is scaled below 450 mV. For V_dd below V_th, bitcells must be sized greatly to retain robustness and large arrays become impractical. The differential 6 T and 8 T designs have the lowest dynamic energy consumption, and the single-ended 6 T design has the lowest leakage. The supply voltage for minimum energy operation depends on cache configuration and can be well above V_th for large caches with low dynamic activity.