Multi-layer interconnect performance corners for variation-aware timing analysis

Parasitic interconnect corner methods are known to be inaccurate. This paper explains the sources of their errors and shows that errors in excess of 22% can occur in the predicted corner delays of a multi-layer stage in the presence of process variations. It is shown that exhaustive corner search methods are infeasible in practice as they have an exponential complexity in terms of required SPICE simulations with respect to the number of layers a stage is routed through. This exponential complexity is reduced to a linear one with a new simulation-based search method with the aid of stage delay properties. The ideas behind the simulation-based methodology are shown to be expandable to an analytical-based multi-layer performance comer location methodology. The simulated best/worst case delays based on these analytical corners produce errors below 4% as compared to the exhaustive search simulation based method.