DocumentCode :
2332202
Title :
Efficient decoupling capacitance budgeting considering operation and process variations
Author :
Shi, Yiyu ; Liu, Chunchen ; He, Lei ; Xiong, Jinjun
Author_Institution :
UCLA, Los Amgeles
fYear :
2007
fDate :
4-8 Nov. 2007
Firstpage :
803
Lastpage :
810
Abstract :
This paper solves the variation-aware on-chip decoupling capacitance (decap) budgeting problem. Unlike previous work assuming the worst-case current load, we develop a novel stochastic current model, which efficiently and accurately captures operation variation such as temporal correlation between clock cycles and logic-induced correlation between ports. The models also considers current variation due to process variation with spatial correlation. We then propose an iterative alternative programming algorithm to solve the decap budgeting problem under the stochastic current model. Experiments using industrial examples show that compared with the baseline model which assumes maximum currents at all ports and under the same decap area constraint, the model considering temporal correlation reduces the noise by up to 5times, and the model considering both temporal and logic-induced correlations reduces the noise by up to 17times. Compared with the model using deterministic process parameters, considering process variation tLej f variation in this paper reduces the mean noise by up to 4times and the 3 sigma noise by up to 13times. While the existing stochastic optimization has been used mainly for process variation purpose, this paper to the best of our knowledge is the first in-depth study on stochastic optimization taking into account both operation and process variations for power network design. We convincingly show that considering operation variation is highly beneficial for power integrity optimization and this should be researched for optimizing signal and thermal integrity as well.
Keywords :
iterative methods; network analysis; optimisation; clock cycles; decoupling capacitance budgeting; deterministic process; iterative alternative programming algorithm; logic-induced correlation; power integrity optimization; power network design; process variations; stochastic current model; stoclmstic optimization; temporal correlation; Capacitance; Clocks; Convolution; Crosstalk; Design optimization; Iterative algorithms; Noise reduction; Semiconductor device noise; Stochastic processes; Stochastic resonance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer-Aided Design, 2007. ICCAD 2007. IEEE/ACM International Conference on
Conference_Location :
San Jose, CA
ISSN :
1092-3152
Print_ISBN :
978-1-4244-1381-2
Electronic_ISBN :
1092-3152
Type :
conf
DOI :
10.1109/ICCAD.2007.4397364
Filename :
4397364
Link To Document :
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