Design of a 1024 bit RSA coprocessor with SPI slave interface

This paper presents the architecture and model of a modular exponentiation hardware for RSA public key cryptography algorithm with a SPI slave interface for on-board peripheral communication. A radix 2 Montgomery modular multiplication hardware based on a systolic implementation was designed. A kogge-stone adder is used to reduce the critical path and improve throughput. Cadence© Encounter RTL Compiler was used to synthesize the RTL code described in Verilog HDL. The coprocessor was implemented with standard cells library from 0.18μm CMOS IBM 7RF technology. The SPI maximum SPI transfer rate is 100 Mb/s. This implementation runs 1024 bit RSA encryption and decryption process in 8.44ms and the throughput of this implementation is 121.269Kbps.