Title :
Process variation compensation with effective gate-width tuning for low-voltage CMOS digital circuits
Author :
Kishiwada, Y. ; Ueda, S. ; Miyawaki, Y. ; Matsuoka, T.
Author_Institution :
Div. of Electr., Electron. & Inf. Eng., Osaka Univ., Suita, Japan
Abstract :
Recently, as CMOS devices become smaller, process variation, especially threshold voltage variation, significantly influences circuit characteristics under lower supply voltage. This paper proposes a process variation compensation technique with effective gate-width tuning as well as body biasing.
Keywords :
CMOS digital integrated circuits; body biasing; gate-width tuning; low-voltage CMOS digital circuits; process variation compensation; threshold voltage variation; CMOS integrated circuits; CMOS technology; Digital circuits; Inverters; Logic gates; Temperature dependence; Tuning; CMOS digital circuits; Process variation compensation; effective gate-width tuning; low-voltage operation;
Conference_Titel :
Future of Electron Devices, Kansai (IMFEDK), 2012 IEEE International Meeting for
Conference_Location :
Osaka
Print_ISBN :
978-1-4673-0837-3
DOI :
10.1109/IMFEDK.2012.6218634
