Short channel continuous model for double-gate junctionless transistors

Author

Cardoso Paz, Bruna ; Pavanello, Marcelo Antonio ; Avila, Fernand ; Cerdeira, Antonio

Author_Institution

Dept. of Electr. Eng., Centro Univ. da FEI, São Bernardo do Campo, Brazil

fYear

2014

fDate

2-4 April 2014

Firstpage

1

Lastpage

6

Abstract

This work aims to present a continuous model of the drain current for short channel double-gate junctionless transistors, from a charge-based model for long channel double-gate devices. The proposed model is based on the influence of the drain bias in the channel potential and the reduction of the effective channel length in saturation regime, for short channel transistors. To model validation it will be used three dimensional numerical simulations.

Keywords

MOSFET; semiconductor device models; channel potential; charge-based model; drain bias; drain current; effective channel length; long channel double-gate devices; saturation regime; short channel double-gate junctionless transistors; short channel transistors; three dimensional numerical simulations; Degradation; Electric potential; Logic gates; Numerical models; Silicon; Threshold voltage; Transistors; junctionless; model; short channel;

fLanguage

English

Publisher

ieee

Conference_Titel

Devices, Circuits and Systems (ICCDCS), 2014 International Caribbean Conference on

Conference_Location

Playa del Carmen

Print_ISBN

978-1-4799-4684-6

Type

conf

DOI

10.1109/ICCDCS.2014.7016158

Filename

7016158