Technological parameters scaling influence on the analog performance of Graded-Channel SOI nMOSFET transistors

Author

Assalti, R. ; Pavanello, Marcelo Antonio ; de Souza, M. ; Flandre, Denis

Author_Institution

Electr. Eng. Dept., Centro Univ. da FEI, São Bernardo do Campo, Brazil

fYear

2014

fDate

2-4 April 2014

Firstpage

1

Lastpage

6

Abstract

This paper aims at analyzing, through two-dimensional numerical simulations and experimental results, the influence of technological parameters downscaling on the analog performance of Graded-Channel FD SOI nMOSFET transistors. Front gate oxide and silicon film thicknesses, channel doping concentration, total channel and lightly doped region lengths have been varied to target the highest intrinsic voltage gain.

Keywords

MOSFET; numerical analysis; semiconductor doping; silicon-on-insulator; analog performance; channel doping concentration; front gate oxide; graded-channel SOI nMOSFET transistors; intrinsic voltage gain; lightly doped region lengths; silicon film thicknesses; technological parameters downscaling; total channel lengths; two-dimensional numerical simulations; Films; Gain; High definition video; Logic gates; Silicon; Transconductance; Transistors; Graded-Channel; SOI nMOSFET; analog parameters; intrinsic voltage gain; technological parameters;

fLanguage

English

Publisher

ieee

Conference_Titel

Devices, Circuits and Systems (ICCDCS), 2014 International Caribbean Conference on

Conference_Location

Playa del Carmen

Print_ISBN

978-1-4799-4684-6

Type

conf

DOI

10.1109/ICCDCS.2014.7016159

Filename

7016159