• DocumentCode
    2333701
  • Title

    Synthesis of Petri nets into FPGA with operation flexible memories

  • Author

    Bukowiec, Arkadiusz ; Adamski, Marian

  • Author_Institution
    Inst. of Comput. Eng. & Electron., Univ. of Zielona Gora, Zielona Góra, Poland
  • fYear
    2012
  • fDate
    18-20 April 2012
  • Firstpage
    16
  • Lastpage
    21
  • Abstract
    In this paper a new method of Petri net array-based synthesis is proposed. The method is based on the structured encoding of places by means of using minimal numbers of bits together with parallel decomposition of a digital system. State machine subnets, which are determined by colors are attached to places and transitions. Colored microoperations which are assigned to places are written into distributed and flexible memory. It leads to realization of a logic circuit in a two-level concurrent structure, where the combinational circuit of the first level is responsible for firing transitions, and the second level memories are used for generation of microoperations. Such an approach allows balanced usage of different kinds of resources available in modern FPGAs.
  • Keywords
    Petri nets; combinational circuits; digital storage; field programmable gate arrays; finite state machines; FPGA; Petri net array-based synthesis; colored microoperations; combinational circuit; logic circuit; operation flexible memories; parallel digital system decomposition; state machine subnets; two-level concurrent structure; Color; Encoding; Equations; Field programmable gate arrays; Logic circuits; Petri nets; Registers;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2012 IEEE 15th International Symposium on
  • Conference_Location
    Tallinn
  • Print_ISBN
    978-1-4673-1187-8
  • Electronic_ISBN
    978-1-4673-1186-1
  • Type

    conf

  • DOI
    10.1109/DDECS.2012.6219016
  • Filename
    6219016