Self-aligned nanostructures by CMOS technology

In this paper, the authors demonstrate a method to produce nanostructures and nanowires with dimensions down to 10nm by a self-alignment process using the standard CMOS spacer technology. In this process, very accurate alignment is achieved because the alignment is not determined by the lithographic tool but by the structures and materials themselves. The spacer technique is commonly used in the fabrication of nanometer transistor and does not require the use of submicron lithographic tools. As illustrated in Figure 1, arrays of polysilicon nanostructures have been fabricated on 8" silicon wafers. These include ultra fine structures down to 20nm with an aspect ratio of 10:1, and 10nm structures with an aspect ratio of 20:1. In this process, very accurate alignment is achieved. The formed polysilicon nanostructures can be used as an etch mask to transfer fine patterns to insulating materials such as silicon nitride (Si₃N₄) which in turns is used as a mask for bulk machining of deep silicon structures as shown in Figure 2. The fabricated polysilicon nanowires were phosphorous doped to characterize the effect of length and diameter on the wire resistance. The resistance of the nanowires was found to increase linearly when varying the wire length from 20 to 500nm where the diameter of the nanowires has a significant impact to the wire resistance when its diameter is less than 50nm.