Design and optimization of integrated low-voltage low-power monolithic CMOS charge pumps

Driven by the proliferation of implantable and self-powered electronic devices, low-voltage, low-power, high-efficiency DC-DC power converters are on high demands. This paper first reviews the state-of-the-arts charge pumps, with focus on power loss minimization, power stage architectures and control signaling. A new four-phase complimentary charge pump is then proposed. By employing the techniques of minimizing the reversion loss and conduction loss and interleaving the power stage sub-cells, the design achieves high efficiency and low ripple voltages without compromising fabrication cost. A sub-threshold clock generator is employed to further reduce the power loss in the controller. The charge pump was designed with IBM 180 nm CMOS process with fully on-chip pumping capacitors. HSPICE simulations show that the charge pump maintains the efficiency above 90% within up to 5 mW power range, with the maximum efficiency of 92.01%. The ripple voltage is also much improved in comparison with its counterparts.