Application of IDDT test towards increasing SRAM reliability in nanometer technologies

Dynamic supply current test method (I_DDT test) in static random access memory (SRAM) cell arrays is addressed in order to unveil weak open defects. Simulations were carried out on a 64-bit SRAM circuit, where several parameters of the I_DDT waveform were monitored. The SRAM circuit was designed in a 90 nm CMOS technology. Efficiency of I_DDT test in unveiling open defects was evaluated and the achieved results were compared for four SRAM arrays with cells of different cell ratio (CR). Moreover, a solution for transformation of the dynamic current to voltage is presented. After the transformation of the current waveform to a voltage waveform, the parameters of the voltage waveform similar to those of the current waveform are easily monitored and evaluated.