Title :
A 512 kb SRAM in 65nm CMOS with divided bitline and novel two-stage sensing technique
Author :
Zheng, Xiang ; Liu, Ming ; Chen, Hong ; Cao, Huamin ; Wang, Cong ; Gao, Zhiqiang
Author_Institution :
Tsinghua Nat. Lab. for Inf. Sci. & Technol., Tsinghua Univ., Beijing, China
Abstract :
This paper focuses on high speed embedded SRAM design, especially on novel circuit technique to improve SRAM access time. A new two-stage sensing scheme which is able to reduce long interconnection metal line delay by transferring differential signals with half swing amplitude has been proposed. Post-layout simulation results show that the long distance signal transmission time has been decreased by 45%. Chip measurement shows the access time has been decreased by 23% at the expense of little area penalty (1.3%) and some read power penalty (about 16%) mainly caused by 2nd-stage sense amplifiers.
Keywords :
CMOS digital integrated circuits; SRAM chips; electric sensing devices; integrated circuit interconnections; 2nd-stage sense amplifiers; CMOS; SRAM access time; SRAM design; chip measurement; circuit technique; differential signals transference; divided bitline; half swing amplitude; interconnection metal line delay; long distance signal transmission time; post-layout simulation; read power penalty; size 65 nm; storage capacity 512 Kbit; two-stage sensing technique; Delay; Layout; Metals; Random access memory; Semiconductor device measurement; Sensors; SRAM; divided bitline; high speed; two-stage sensing;
Conference_Titel :
Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2012 IEEE 15th International Symposium on
Conference_Location :
Tallinn
Print_ISBN :
978-1-4673-1187-8
Electronic_ISBN :
978-1-4673-1186-1
DOI :
10.1109/DDECS.2012.6219052
