Impact of unrealistic worst case modeling on the performance of VLSI circuits in deep sub-micron CMOS technologies

The impact of process fluctuations on the variability of deep sub-micron (DSM) VLSI circuit performances is investigated in this paper. In particular, we show that, as process dimensions scale down in the sub half-micron region, the relative weight of process variability tends to increase, thus wearing down a nonnegligible portion of the benefits that are expected from minimum feature size scaling. Therefore, in order to better exploit the advance of process technology, it is essential to adopt a realistic approach to worst case modeling, as in the assigned probability technique (APT) (Dal Fabbro et al, Proc. 32nd ACM/IEEE Design Automation Conf., pp. 702-6, 1995). The application of the APT technique to a 16-bit ripple-carry adder designed in 0.35 μm, 0.25 μm and 0.18 μm CMOS technologies with a power supply ranging from 3.3 V down to 1 V demonstrates how the manufacturability of DSM designs is going to be a vital factor for the successful implementation of high performance or low-power systems in 0.18 μm and lesser technologies