DocumentCode :
2334553
Title :
SPC09-3: Hardware-Accelerated Simulation Tool for End-to-End Communication Systems
Author :
Lin, V.S. ; Pansatiankul, D.E.
Author_Institution :
Aerosp. Corp., Los Angeles, CA
fYear :
2006
fDate :
Nov. 27 2006-Dec. 1 2006
Firstpage :
1
Lastpage :
5
Abstract :
We present a hardware/software co-simulation tool for computation-intensive, end-to-end communication systems. The tool uses commercial field-programmable gate arrays (FPGAs), together with a high-level programming language, to accelerate the total simulation run time. This paper not only describes the design and implementation aspects of the tool, but also presents the laboratory demonstration of the system. Based on the test results, we compare the real-time throughput performance of FPGA-based co-simulation with that of conventional software-only simulation.
Keywords :
computer networks; field programmable gate arrays; computation-intensive systems; end-to-end communication systems; field programmable gate arrays; hardware-accelerated simulation tool; hardware/software co-simulation tool; high level programming language; real-time throughput performance; software-only simulation; Acceleration; Communication system software; Computational modeling; Computer languages; Field programmable gate arrays; Hardware; Laboratories; Software testing; Software tools; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Global Telecommunications Conference, 2006. GLOBECOM '06. IEEE
Conference_Location :
San Francisco, CA
ISSN :
1930-529X
Print_ISBN :
1-4244-0356-1
Electronic_ISBN :
1930-529X
Type :
conf
DOI :
10.1109/GLOCOM.2006.582
Filename :
4151212
Link To Document :
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