Reducing silicon usage during technology development-a variance analysis approach

During the development of semiconductor process flows, various process and device design alternatives must be evaluated to allow identification of the best candidate flow. In a development fab, this comparison is made in the presence of inherent manufacturing variation together with the variation associated with changes such as aggressive lithographic scaling and adoption of new unit processes. In this environment of high process variability, it is difficult to identify the best performance recipe from a set of candidate recipes. The problem is further exacerbated by the need to minimize silicon usage to lower development costs. In this paper, we describe a method to enhance the ability to detect the impact of design alternatives on device performances. The method uses simple statistical concepts to first account for and then adjust for the various sources of variation. The approach has two advantages. First, it significantly reduces the amount of silicon required for recipe comparison. The method allows us to evaluate flows based on as little as half- or quarter-wafer allocation without compromising experimental resolution. Second, the approach decouples the problem of evaluating design alternatives for performance improvement from the problem of controlling the higher variation associated with new processes. Once a good candidate recipe has been identified with the proposed method, it may be transferred to a more expensive but tightly controlled fab for volume production