Full-custom design and characterization of a phase locked loop — DLS565 using 0.5um CMOS technology

Author

Atendido, Kenneth Martin C. ; Co, Justin Daniel C. ; Navarro, Jose Gianmarco B. ; Garcia, Pamela Candice H. ; Abad, Alexander C.

Author_Institution

Electron. & Commun. Eng. Dept., De La Salle Univ. Manila, Manila, Philippines

fYear

2014

fDate

12-16 Nov. 2014

Firstpage

1

Lastpage

6

Abstract

The DLS565 is a Phase-locked loop (PLL) Integrated Circuit (IC) design project simulated on all process corner libraries (TT, FF, SS, FS, SF) using 0.5um CMOS technology. The final IC design layout of the PLL without bonding pads covers approximately 0.46mm × 0.5mm. The parameters of the DLS565 were measured and compared to the commercially available LM565C and NE565. It operates with a supply voltage of ±2.5 V with a maximum power dissipation of approximately 22 mW. DLS565 was able to capture frequencies as low as 15Hz and as high as 1.12MHz.

Keywords

CMOS analogue integrated circuits; integrated circuit layout; phase locked loops; DLS565 using; FF libraries; FS libraries; IC design layout; LM565C; NE565; PLL integrated circuit design project; SF libraries; SS libraries; TT libraries; full-custom design; phase locked loop; process corner libraries; size 0.5 mum; Capacitors; Cutoff frequency; Detectors; Layout; Phase locked loops; Transistors; Voltage-controlled oscillators; Lowpass Filter (LPF); Phase Detector (PD); Phase-Locked Loop (PLL); Voltage-Controlled Oscillator (VCO);

fLanguage

English

Publisher

ieee

Conference_Titel

Humanoid, Nanotechnology, Information Technology, Communication and Control, Environment and Management (HNICEM), 2014 International Conference on

Conference_Location

Palawan

Print_ISBN

978-1-4799-4021-9

Type

conf

DOI

10.1109/HNICEM.2014.7016240

Filename

7016240