Implementation of bit-serial recursive digital filters

A single-chip digital filter capable of realizing a single class of transfer function with programmable cutoff frequencies, stopband attenuation, and passband ripple has been designed and implemented. The filter is implemented using a pipelined bit-serial two´s-complement arithmetic architecture. Six different recursive digital filter structures were analyzed to determine the minimum signal and coefficient wordlengths required to obtain the same performance with each of the filters. This information was then used to estimate the maximum sample rate possible and the number of gates that would be required to implement each filter structure using the same gate array fabrication technology. The bilinear LDI digital filter chosen for implementation required the least gates for an architecture in which on pipelined bit-serial multiplier is shared throughout the filter.<>