Title :
A SBST strategy to test microprocessors´ Branch Target Buffer
Author :
Bernardi, P. ; Ciganda, L. ; Grosso, M. ; Sanchez, E. ; Reorda, M. Sonza
Author_Institution :
Dipt. di Autom. e Inf., Politec. di Torino, Torino, Italy
Abstract :
A Branch Target Buffer (BTB) is a mechanism to support speculative execution in order to overcome the performance penalty caused by branch instructions in pipelined microprocessors. Being an intrinsically fault tolerant unit, it is hard to achieve a good fault coverage resorting to plain functional testing methods. In this paper we analyze the causes for low functional testability and propose some techniques able to effectively face these issues. In particular, we describe a strategy to perform SBST on fully associative BTB units. The unit´s general structure is analyzed, a suitable test program is proposed and the strategy to observe the test responses is explained. Feasibility and effectiveness of the proposed approach are shown on a MIPS-like processor.
Keywords :
buffer circuits; fault tolerance; microprocessor chips; MIPS-like processor; SBST strategy; branch instruction; fault tolerant unit; functional testability; functional testing method; pipelined microprocessor; suitable test program; test microprocessor branch target buffer; Circuit faults; Clocks; Microprocessors; Pipelines; Prediction algorithms; Radiation detectors; Testing; SBST; branch prediction; branch target buffer; microprocessors; testing;
Conference_Titel :
Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2012 IEEE 15th International Symposium on
Conference_Location :
Tallinn
Print_ISBN :
978-1-4673-1187-8
Electronic_ISBN :
978-1-4673-1186-1
DOI :
10.1109/DDECS.2012.6219079
