On the use of assertions for embedded-software dynamic verification

Assertion-based verification (ABV) affirmed as an effective methodology for functional verification, i.e., design specification conformance, of embedded systems. Academia and industry have throughly investigated formal ABV for high-budget or safety-critical hardware and software projects, while the scalability of dynamic ABV has led to the introduction of standard languages and commercial tools addressing hardware design verification, emulation, and silicon debug. However, up to now, there were only limited studies concerning the application of dynamic ABV to embedded-software design and verification flow. We propose an analysis aiming to bridge such a gap. In particular, we illustrate how dynamic ABV can integrate and improve the various stages of the embedded-software verification flow. The analysis leads us to develop a comprehensive ABV environment that integrates the still missing automatic synthesis of executable checkers for embedded software. Experiments show that the proposed environment reduces the verification-team efforts and makes dynamic ABV practical for embedded-software design.