Phase locked loop with extended range phase detector

In many synchronous communications systems, reproduction of the carrier frequency of received signal and filtration of the phase jitter are important basic operations. For example, in Token Ring Data Networks, at each node the data and the carrier need to be recovered, the phase filtered, the data processed, encoded and retransmitted to the downstream node. For input signals impaired by phase wander due to thermal effects and by phase jitter, the aims are to acquire frequency and phase, to track frequency wander, to attenuate the phase jitter and to hold the tracking loop in lock-state, in order to keep the Bit Integrity Count (BIC). The requirements of jitter attenuation and maintenance of BIC lead to conflicting requirements when a conventional phase locked loop with conventional phase detector is used to achieve these aims. To overcome this conflict, a novel algorithm for phase detection has been proposed, and expanded and analyzed in this paper. It is referred to as the Extended Range Phase Detector (ERPD), designed to handle continuous inputs and reference signals with phase jitter, in presence of additive noise. It has an extended detection period of N/sub C/ times 2/spl pi/; N/sub C/ being design parameter. It includes, in addition to the CPD, a component which senses and counts full cycles of phase excursion. A PLL which contains a ERPD is called an Extended Range PLL (ERPLL). The ERPLL enables flexibility in design of the loop according to the applications, for owing to the ERPD, it is relieved of the interconnection between phase filtration ability and BIC maintenance. Its performance in terms of frequency and phase acquisition, phase filtration, immunity to additive noise and keeping of BIC is presented, based on analysis and simulation.