Memory requirements and simulation platform for the implementation of the H.264 encoder modules

In this paper, we propose a real-time platform for the H.264 CODEC with a memory management method, in which we use a preloading mechanism in order to reduce access to external memory. The platform uses an external DDR2 memory (to record the sequence images) and an intelligent memory controller to read the external memory periodically to load another local memory by the macroblocks (of different sizes) for the processing modules of the H.264 encoder, depending on image manipulation and chosen processing mode. The proposed intelligent controller is tested on a Xilinx virtex5-ML501 platform with multiple internal and external components, including a DDR2 memory. Similarly, the proposed memory controller is well adapted to future System-on-Chip applications with restricted memory-bandwidth.