DocumentCode :
233729
Title :
Tutorial T3B: Engineering Change Order (ECO) Phase Challenges and Methodologies for High Performance Design
Author :
Rangarajan, Sampath ; Chakrabarti, P. ; Sahais, Sourav ; Datta, Amitava ; Subramanya, A.
fYear :
2014
fDate :
5-9 Jan. 2014
Firstpage :
7
Lastpage :
8
Abstract :
Summary form only given. Engineering Change Order or ECO phase is always challenging for any family of chip design. High Performance Microprocessors are largest and most complex overall design within Semiconductor Industry as a whole. To add further, there are additional design and methodology challenge related to bleeding edge of process nodes. Hence, current and future microprocessor design requires a set of well planned and innovative methodologies to cater to the ECO requirement when the race to the finishing line begins! This tutorial is organized into following four key sections. Apart from that, there will be a brief preview section and a real scenario-based learning section towards the end.
Keywords :
circuit CAD; integrated circuit design; microprocessor chips; monolithic integrated circuits; CAD; ECO readiness indicator; ECO variants; chip design; engineering change order phase; high performance microprocessors; post ECO design closure; semiconductor industry; Computer science; Design automation; Engines; Microprocessors; Optimization; Timing; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design and 2014 13th International Conference on Embedded Systems, 2014 27th International Conference on
Conference_Location :
Mumbai
ISSN :
1063-9667
Type :
conf
DOI :
10.1109/VLSID.2014.118
Filename :
6733092
Link To Document :
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