Analytical Modeling of 3D Stacked IC Yield from Wafer to Wafer Stacking with Radial Defect Clustering

Current yield estimation models for 3D Stacked ICs manufactured using wafer-to-wafer stacking ignore defect clustering and assume a uniform distribution of defective dies on each wafer. Recent experiments based on carefully simulated wafer defect maps and validated by actual silicon data have shown that the clustering of manufacturing defects can have a major impact on actual 3D-SIC yields. Traditionally modeled yield estimates can be pessimistic by as much as 50%. However, no new analytical models have as yet been developed to account for this defect clustering effect. We present and validate the first 3D-SIC yield model that incorporates the impact of the radial clustering of defects on wafers. This major contributor to defect clusters on wafers can be directly included in analytical models using a few easy to measure spatial measures of wafer yield. Our new model is validated using synthesized wafer defect maps from proven radial defect models, as well as actual silicon wafer defect map data. The results presented here show that the models accurately capture much of the impact of defect clustering on 3D-SIC yields, and can allow the cost trade-offs associated with 3D-SIC manufacturing to be more easily and accurately estimated early in the design phase.