Techniques to Improve the Efficiency of SAT Based Path Delay Test Generation

Author

Bian, Kaigui ; Walker, Duncan M. Hank ; Khatri, Sunil P.

Author_Institution

Dept. of Electr. & Comput. Eng., Texas A&M Univ., College Station, TX, USA

fYear

2014

fDate

5-9 Jan. 2014

Firstpage

50

Lastpage

55

Abstract

Boolean Satisfiability (SAT) solvers have been used to speed up test pattern generation. In this work, several techniques to speed up SAT-based path delay test generation are presented. We demonstrate that these techniques: circuit simplification, Dynamic SAT Solving, Circuit Observability Don´t Cares and Approximate Observability Don´t Cares, significantly improve the efficiency of path delay test generation. The effectiveness of these techniques has been demonstrated on benchmark and industrial designs.

Keywords

benchmark testing; circuit testing; computability; delay circuits; observability; Boolean satisfiability solver; approximate observability don´t cares; benchmark; circuit observability don´t cares; dynamic SAT solving; path delay test generation; Algorithm design and analysis; Circuit faults; Compaction; Decision support systems; Delays; Logic gates; Observability; observability; path delay test; satisfiability;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design and 2014 13th International Conference on Embedded Systems, 2014 27th International Conference on

Conference_Location

Mumbai

ISSN

1063-9667

Type

conf

DOI

10.1109/VLSID.2014.16

Filename

6733105