Techniques to Improve the Efficiency of SAT Based Path Delay Test Generation

Boolean Satisfiability (SAT) solvers have been used to speed up test pattern generation. In this work, several techniques to speed up SAT-based path delay test generation are presented. We demonstrate that these techniques: circuit simplification, Dynamic SAT Solving, Circuit Observability Don´t Cares and Approximate Observability Don´t Cares, significantly improve the efficiency of path delay test generation. The effectiveness of these techniques has been demonstrated on benchmark and industrial designs.