CryptIP: An Approach for Encrypting Intellectual Property Cores with Simulation Capabilities

Modern complex digital designs are becoming feasible due to the use of System on Chip design techniques in which designers use Intellectual Property (IP) cores and their own glue logic to create a design. A major limitation in testing such designs is that the designer is restricted to use the test vectors provided by the IP core provider. For a designer to use their own test vectors, the designer must have full gate level access, not just the functional access, to the implementation of the IP core. IP providers are often reluctant to provide such access for proprietary reasons. This paper proposes a method of encrypting a logic circuit such that the structural information of the design is preserved but the gate/component functionalities are encrypted. The encryption is such that a designer can perform logic as well as fault simulation on the encrypted circuit without deducing the gate/component functionalities of the gates/components in the circuit. This gives the designer the capability to design the logic around the IP core as well as use its own test vectors and to target desired fault coverage. The details of the encryption method and the complexity of decryption are discussed in the paper. The paper also shows how logic and fault simulation can be performed on the encrypted circuit and the performance of such simulation is comparable to simulating the un-encrypted circuit.