• DocumentCode
    233786
  • Title

    A Cube-Aware Compaction Method for Scan ATPG

  • Author

    Jha, Somesh ; Chandrasekar, Karthik ; Weixin Wu ; Sharma, Ritu ; Sengupta, Sabyasachi ; Reddy, S.M.

  • Author_Institution
    Intel Corp., Santa Clara, CA, USA
  • fYear
    2014
  • fDate
    5-9 Jan. 2014
  • Firstpage
    98
  • Lastpage
    103
  • Abstract
    We propose a test-cube aware dynamic compaction method for reducing the test set size generated by scan ATPG. In the initial phase of ATPG, when the generated test cubes are significantly compatible, we start with a local cube merging approach. Then, we switch to a compacted cube-generation approach, when the compatibility of test cubes decrease. We propose efficient heuristics for merging test cubes and writing them out during the cube-merging phase. We introduce a novel reasoning analysis technique to learn cube-independent untestable faults and, avoid targeting them repeatedly during the compacted-cube generation phase. On latest Intel microprocessor designs, we are able to achieve up to 2.3X compaction with 20% run-time over-head, on top of on-chip hardware compression.
  • Keywords
    automatic test pattern generation; Intel microprocessor designs; compacted-cube generation phase; on-chip hardware compression; reasoning analysis technique; scan ATPG; test-cube aware dynamic compaction method; Automatic test pattern generation; Circuit faults; Cognition; Compaction; Fault diagnosis; Merging; Vectors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design and 2014 13th International Conference on Embedded Systems, 2014 27th International Conference on
  • Conference_Location
    Mumbai
  • ISSN
    1063-9667
  • Type

    conf

  • DOI
    10.1109/VLSID.2014.24
  • Filename
    6733113