A Novel Low Power Error Detection Logic for Inexact Leading Zero Anticipator in Floating Point Units

In floating point addition unit, adder and normalization decides the critical path delay. By predicting the shift amount prior to the adder´s output the delay introduced by the normalization can be reduced. This prediction is done using a technique called Leading Zero Anticipator (LZA). LZA algorithms are divided into exact and inexact categories. Most of the existing algorithms are inexact in nature which predicts the shift amount with a possible error of 1 bit. So, these inexact LZA algorithms need an error detection circuit. This paper proposes an error detection logic implemented in parallel with adder and using a part hardware of LZA resulting in reduction of both area and power consumption by 35%-39% and 44%-48% respectively when compared with that of general LZA and error detection circuit.