A 500 mV to 1.0 V 128 Kb SRAM in Sub 20 nm Bulk-FinFET Using Auto-adjustable Write Assist

It is essential to scale voltage to the lowest possible value to get maximum power saving while ensuring correct write operation in SRAMs. Writing on the bit-cell becomes tough as one moves to low periphery and array voltages. In some design cases the array voltage is kept 30 to 40 % higher than the periphery voltage or the word-line is lowered for read assist [1], deteriorating the write margin further. At low voltages, write assist technique such as negative bit-line has been shown to be more robust as compared to the other techniques [2]. However at high voltages this technique comes along with a problem of degraded reliability and data corruption on the half selected and unselected bit cells as they turn on due to excessive negative voltages on the source [3]. To overcome the same, we propose, an auto-adjustable negative bit-line write assist circuit which uses a combination of an array of capacitances, voltage dependent tracking circuit and hard reconfigurability to create a suitable negative voltage level according to the operating voltage, ranging from 500 mV to 1.0 V. The same has been implemented in a test chip for high-density (HD) and high speed (HS) 128 Kb SRAMs in a sub-20 nm bulk FinFET process, enabling the write operation successfully till 300 mV. The HS cut is able to run at more than 4.0 GHz while the HD cut achieves a speed of 3.5 GHz at -40 ⁰C and operating voltage of 1 V. While the operating frequency achieved at 500 mV is above 2.0 GHz at -40 ⁰C. At the worst PVT corners the minimum negative voltage on the bit line goes to -160 mV while at higher voltages it is greater than -180 mV level mitigating all the reliability issues and writing on the 6σ worst bit. The area impact is less than 10 %.