DocumentCode
2338149
Title
AN IMPLICIT ENUMERATION ALGORITHM TO GENERATE TESTS FOR COMBINATIONAL LOGIC CIRCUITS
Author
Goel, Prabhakar
fYear
1995
fDate
27-30 Jun 1995
Firstpage
337
Keywords
Circuit faults; Circuit testing; Combinational circuits; Data systems; Error correction; Linear programming; Logic circuits; Logic design; Logic testing; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Fault-Tolerant Computing, 1995, Highlights from Twenty-Five Years., Twenty-Fifth International Symposium on
Print_ISBN
0-8186-7150-5
Type
conf
DOI
10.1109/FTCSH.1995.532656
Filename
532656
Link To Document