DocumentCode :
233826
Title :
Hardware Implementation of Real-Time, High Performance, RCE-NN Based Face Recognition System
Author :
Sardar, S. ; Babu, K. Ajay
Author_Institution :
Defence R&D Organ., New Delhi, India
fYear :
2014
fDate :
5-9 Jan. 2014
Firstpage :
174
Lastpage :
179
Abstract :
Hardware implementation of a real-time, highly accurate face recognition system (FRS) is proposed in this correspondence. Face images are acquired from a CMOS sensor camera connected to Field Programmable Gate Array (FPGA) based reconfigurable hardware board using Cam Link interface. We used contrast limited adaptive histogram equalization (CLAHE) for image contrast enhancement, discrete wavelet transform (DWT) to remove variable illumination & select appropriate subband and principal component analysis (PCA) with 35 principal components which is optimized for performance and speed. Finally, Restricted Coulomb Energy (RCE) based neural network (NN) classifier is used for face recognition. We have implemented the RCE based NN in FPGA and thus utilized the inherent parallelism effectively which is not possible with NN software implementation. The performance of our implementation is superior than face recognition software and hardware implementations, which are targeted to achieve higher recognition accuracy at faster rate using minimum computational resources. Our system recognizes a single image in real-time i.e. within 18 ms corresponding to 37 frames per second image capture. We have verified our proposed system with multiple standard face databases as well as using our own face data repository.
Keywords :
CMOS image sensors; discrete wavelet transforms; face recognition; field programmable gate arrays; image classification; lighting; neural nets; principal component analysis; CLAHE; CMOS sensor camera; CamLink interface; FPGA; PCA; RCE-NN based face recognition system; appropriate subband selection; contrast limited adaptive histogram equalization; discrete wavelet transform; face data repository; face image acquisition; field programmable gate array based reconfigurable hardware board; hardware implementation; high performance face recognition system; image contrast enhancement; minimum computational resources; principal component analysis; real-time face recognition system; restricted Coulomb energy based neural network classifier; standard face databases; variable illumination removal; Face; Face recognition; Field programmable gate arrays; Hardware; Histograms; Neurons; Principal component analysis; CLAHE; CMOS; CamLink; DWT; FPGA; FRS; NN; PCA; RCE;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design and 2014 13th International Conference on Embedded Systems, 2014 27th International Conference on
Conference_Location :
Mumbai
ISSN :
1063-9667
Type :
conf
DOI :
10.1109/VLSID.2014.37
Filename :
6733126
Link To Document :
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