Stanford Telecom VLSI design of a convolutional decoder

The authors describe the novel hardware and speed-efficient architectural features of a recent Stanford Telecom VLSI implementation of a 20-Mb/s convolutional decoder using 1.5-μm CMOS technology. The chip offers a selection of convolutional codes, including the (2,1) K=7 code commonly used in satellite communications, high-rate punctured versions of the code, and a (2,1) K=6 code included for requirements of backward compatibility. In addition, the implementation allows integration within a blocked TDMA (time-division multiple-access) structure (burst-mode operation), as well as the continuous channels most often associated with such codes. Other features include optional use of external metrics and automatic self-synchronization. The architecture of the decoder makes a novel use of a rotating memory principle that allows three processes to read and write four areas of memory in a parallel and continuous fashion. The technique allows a longer path decoding constraint length to be achieved for the utilized memory or, alternatively, reduces the amount of chip area allocated to memory and random logic. It also has the virtue of making the TDMA integration into a simple reset operation