A Test Pattern Generation Method Based on Fault Injection for Logic Elements of FPGA

In this paper, we present a test pattern generation method based on fault injection for logic elements of FPGAs (Field Programmable Gate Arrays). This method is able to perform fault diagnosis for stuck-at-0 and stuck-at-1 faults, which can locate logic resource faults in the logic elements of FPGA. We use EP2C8Q208C8N´s LE (Logic Element) of Altera as the object to generate the test pattern, work out the test circuit and synthesis them by Quartus II. Finally, the test circuit is injected with stuck-at-0 and stuck-at-1 faults and the test patterns are generated by using SPICE.