Configurable Systolic Matrix Multiplication

Matrix multiplication is an important basic operation that is used in a vast range of applications like image processing and DSP. The design and implementation of a new matrix multiplication module is the main focus of this paper. Our proposed matrix multiplier hardware can easily be re-configured in order to accept any pair of input matrices that are mathematically allowed to multiply. The proposed hardware not only is able to multiply both square and non-square matrices, but it also utilizes a scalable systolic architecture to enhance the computation speed in terms of clock cycles compared to a previously established work in this area. Non-square multiplication and re-configurability of the proposed matrix multiplier make it capable of being used in higher level system applications such as a filter. The corresponding RTL code was developed, compiled, and simulated using the SystemC library. The implemented design is also synthesized for different matrix dimensions and the cost of hardware in terms of basic logic elements is reported.