DocumentCode
2339161
Title
Discrete-time integrated circuits for chaotic communication
Author
Delgado-Restituto, Manuel ; Rodríguez-Vázquez, Angel
Author_Institution
Centro Nacional de Microelectron., Seville Univ., Spain
Volume
2
fYear
1997
fDate
9-12 Jun 1997
Firstpage
1073
Abstract
This paper gives design considerations for the synthesis of analog discrete-time encoder-decoder pairs based on digital filter structures with overflow non-linearity. Simulation results from an integrated prototype using switched-capacitor techniques and designed in a 0.8 μm CMOS technology are presented to validate the suitability of these systems for information encryption
Keywords
CMOS analogue integrated circuits; chaos; codecs; cryptography; discrete time systems; switched capacitor networks; CMOS technology; analog discrete-time encoder-decoder pairs; chaotic communication; discrete-time integrated circuits; information encryption; overflow non-linearity; switched-capacitor techniques; CMOS technology; Chaotic communication; Cryptography; Decoding; Digital filters; Integrated circuit synthesis; Nonlinear equations; Signal synthesis; Transmitters; Virtual prototyping;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on
Print_ISBN
0-7803-3583-X
Type
conf
DOI
10.1109/ISCAS.1997.621931
Filename
621931
Link To Document