• DocumentCode
    233936
  • Title

    Delete and Correct (DaC): An Atomic Logic Operation for Removing Any Unwanted Wire

  • Author

    Xing Wei ; Tak-Kei Lam ; Xiaoqing Yang ; Wai-Chung Tang ; Yi Diao ; Yu-Liang Wu

  • Author_Institution
    Dept. of Comput. Sci. & Eng., Chinese Univ. of Hong Kong, Shatin, China
  • fYear
    2014
  • fDate
    5-9 Jan. 2014
  • Firstpage
    375
  • Lastpage
    380
  • Abstract
    In a deep sub-micron technology era where wiring delays are more dominating, being able to remove any undesirable signal wire (e.g. too long, hardly routable, or highly delay-violating) with chip functionality unchanged should be quite useful for circuit optimizations. Rewiring is a logic transformation technique through which a target wire can be removed by adding its alternative logics with functionality intact. However, normally the rewiring rate (percentage of original circuit wires being removable by rewiring) for most techniques is only 30% to 40% for optimized circuits in the past. A recently proposed error cancellation based rewiring scheme FECR has finally achieved a breaking rewiring rate of 95% however with an impractical algorithm complexity of (O(n5)). In this paper we propose a Delete and Correct (DaC) rewiring in terms that a target wire is deleted first then the circuit is corrected by adding just one or two new wires. This DaC technique, besides being much more efficient (O(n2)), can also achieve a near complete rewiring rate (over 95%) even for fully optimized circuits. Experimentally, the runtime is largely reduced by 32 times compared to FECR. As any logic gate can also be removed through exercising this DaC operation repeatedly, perhaps some originally involved cell-based logic synthesis flow could now be rebuilt atop this simple, atomic (and universal) wiring-based logic operation with better performance predictability.
  • Keywords
    logic gates; atomic logic operation; delete and correct rewiring; logic gate; logic synthesis flow; runtime; unwanted wire removal; Automatic test pattern generation; Complexity theory; Delays; Logic gates; Routing; Wires; Wiring; Cut Enumeration; Error Cancellation; Error Cut; Error Frontier; Logic Rewiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design and 2014 13th International Conference on Embedded Systems, 2014 27th International Conference on
  • Conference_Location
    Mumbai
  • ISSN
    1063-9667
  • Type

    conf

  • DOI
    10.1109/VLSID.2014.71
  • Filename
    6733160