A low OSR multi-bit cascaded delta-sigma modulator

A wide bandwidth 2-1 order cascaded delta sigma modulator with multi-bit internal quantizer is introduced. In order to prevent the distortion caused by the mismatch between the internal multi-bit ADC and multi-bit DAC, a special structure is employed to get rid of using the multi-bit DAC in feedback path. The main topology is a 2-1 order cascaded structure. This 3^rd order architecture uses switched capacitor based loop filter and a 7-level internal quantizer in the 2^nd stage. Buffered amplifier is employed to drive high capacitive load without increasing power dissipation in switched capacitor circuit. Simulated under 1.8 V source voltage driven, this modulator achieves 95 dB SNR over a bandwidth of 250 kHz when clock frequency is 12.5 MHz (32 over-sampling ratio).