PFD output monitoring for RF PLL BIST

With devices operating at ever increasing speed, high resolution RF circuit performances are rapidly becoming non measurable even with the use of RF dedicated testers at affordable costs. This work deals with the development of BIST techniques for RF PLLs. Our aim is to find test measures that are highly correlated to performances that are too costly to measure on-chip and/or on-tester, in order to reduce test time and resources for production test while maintaining standard quality. A BIST output is typically a Go/No-Go output digital signal (most often associated with a structural test). In this work, we will consider as BIST outputs low frequency outputs from embedded monitors (BIST sensors) that can be used by the tester for the evaluation of circuit performances by means of regression functions (Alternate Test). In particular, we will consider monitoring the output of the phase frequency detector (PFD) for PLL BIST purposes. Our case-study is a 65 nm CMOS RF PLL designed and manufactured at ST Microelectronics.