Performance Optimization and Parameter Sensitivity Analysis of Ultra Low Power Junctionless MOSFETs

The paper investigates the impact of doping concentration on the performance of Ultra Low Power (ULP) Junctionless Double Gate MOSFETs. Results show that intrinsic delay is reduced by 69% and on-off current ratio is increased by 2.5 times when junctionless transistors are designed with a doping concentration of 5×10¹⁸ cm^-3 as compared to those designed with 3×10¹⁹ cm^-3. Additional advantage of operating at 5×10¹⁸ cm^-3 is the significant reduction in the parameter sensitivity values of on-current, off-current and intrinsic delay. JL devices exhibit least sensitivity towards gate length in comparison to other parameters. The results when compared with inversion mode and under lap devices highlight the advantages of junctionless devices for ULP logic technology applications.