Timing characterization and layout of a low power differential C2MOS flip flop in 0.35μm technology

The chip developed (UltraSonic Low Voltage SAP for General Electric Medical) in co-operation of AEL (Advenced Electronic Laboratory university of Batna) and MAZ Brandenburg has been produced with 0.35 mum CMOS technology from AMS. The receiver sub-aperture processor is designed to handle the information from ultra-sonic transducer elements inside the probe handler. It performs basic analogue signal processing, and passes the output signal to a host system via a coax cable. Violations in the timing constraints of a clocked flip flop can cause a synchronous system to malfunction. The effects of variations in the power supply voltage (VDD) on the timing characteristics of registers are investigated in this paper. The relations of the setup/hold time and data propagation delay to power supply variations are demonstrated for different cases (nominal case, best case and worst case).