Title :
An Optimized Design of Reversible Quantum Comparator
Author :
Phaneendra, P. Sai ; Vudadha, Chetan ; Sreehari, V. ; Srinivas, M.B.
Author_Institution :
Birla Inst. of Technol. & Sci. - Pilani, Hyderabad, India
Abstract :
Reversible computing has emerged as promising technology having its applications in emerging technologies like quantum computing, optical computing etc. This paper presents a reversible comparator based on prefix tree grouping methodology. The proposed design is realized by cascading three stages. The first stage is a 1-bit reversible comparator which generates ´greater´ and ´equal´ signals of that operand bit. These signals are combined using prefix tree grouping logic to generate final ´greater´ and ´equal´ signals. Using these final ´greater´ and ´equal´ signals, ´lesser´ signal is generated in the third stage. The design is optimized in quantum level for efficient performance in all the cost metrics. The proposed 64-bit comparator design results in 14.3% reduced quantum delay, 7.8% reduced quantum cost and 25% reduced garbage outputs when compared with the best existing design of prefix based comparator.
Keywords :
comparators (circuits); trees (mathematics); cost metrics; optical computing; prefix tree grouping logic; quantum computing; quantum level; reversible computing; reversible quantum comparator design; word length 1 bit; word length 64 bit; Bismuth; Delays; Design methodology; Equations; Logic gates; Optical computing; Quantum computing; Comparator; Prefix grouping; Quantum computing; Reversible logic;
Conference_Titel :
VLSI Design and 2014 13th International Conference on Embedded Systems, 2014 27th International Conference on
Conference_Location :
Mumbai
DOI :
10.1109/VLSID.2014.103