DocumentCode :
234041
Title :
Light Load Efficiency Improvement in High Frequency DC-DC Buck Converter Using Dynamic Width Segmentation of Power MOSFET
Author :
Mary, N. J. Metilda Sagaya ; Maity, Avisek ; Patra, Abani
Author_Institution :
Electr. Eng., IIT Kharagpur, Kharagpur, India
fYear :
2014
fDate :
5-9 Jan. 2014
Firstpage :
563
Lastpage :
568
Abstract :
This work presents a dynamic width segmentation scheme of the power MOSFETs to improve the light load efficiency in high frequency DC-DC converters. The proposed scheme first senses the load current and decides the maximum number of power MOSFET segments to be turned ON. In order to sense the load current accurately over a wide range, an improved current sensing method is also suggested. The proposed scheme is designed and simulated in a 0.5 μm Bi-CMOS technology. To validate its effectiveness, an integrated system is designed using a monolithic voltage mode, synchronous DC-DC buck converter topology switching at 20 MHz. Only the passive components (L=330 nH and C=2.2 μF) are the off-chip components. The input voltage Vin lies in the range of 2.7 V-5.5 V which is quite suitable for Li-ion or Ni-Cd battery operated applications. The output voltage is targeted at 1.2 V and maximum load current specification is 600 mA. The whole power MOSFET is segmented into 16 equal parts and a signal conditioning loop decides the number of active segments dynamically based on the load current. Simulation result shows that at the lightest load of 10 mA, the power efficiency of the converter with and without the dynamic width segmentation scheme is 40% and 19.5% respectively. This shows an efficiency improvement of nearly 103% at the lightest load of 10 mA.
Keywords :
BiCMOS integrated circuits; DC-DC power convertors; power MOSFET; BiCMOS technology; current 10 mA; current 600 mA; current sensing method; dynamic width segmentation; high frequency DC-DC buck converter; light load efficiency improvement; load current; monolithic voltage mode; off-chip components; passive components; power MOSFET; signal conditioning loop; size 0.5 mum; synchronous DC-DC buck converter topology switching; voltage 2.7 V to 5.5 V; Logic gates; MOSFET; Power harmonic filters; Sensors; Signal generators; Topology; Dynamic width segmentation; control signal generator; input current sensing; signal conditioning;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design and 2014 13th International Conference on Embedded Systems, 2014 27th International Conference on
Conference_Location :
Mumbai
ISSN :
1063-9667
Type :
conf
DOI :
10.1109/VLSID.2014.104
Filename :
6733193
Link To Document :
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