An Adaptive Body-Biased Clock Generation System in 28nm CMOS

An adaptive forward body biasing technique is implemented in a clock generation and distribution test chip for memory interface applications to enable wide-range and high-fidelity operation. The proposed clock generation system employs a self-body-biased ring voltage-controlled oscillator (VCO) in a phase-locked loop (PLL) to adaptively adjust device body voltages over process and temperature variations. Moreover, a differential body-biasing technique incorporated in a duty cycle corrector (DCC) achieves effective correction range with minimal power overhead. The adaptive self-body-biasing technique extends PLL frequency locking range by more than 20 percent while reducing power supply induced jitter (PSIJ) by maximum 25 percent for increased yield and reliable operation.