Title :
A reconfigurable FPGA implementation of an LDPC decoder for unstructured codes
Author :
Hosseini, S. M Ehsan ; Chan, Kheong Sann ; Goh, Wang Ling
Author_Institution :
Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore
Abstract :
This paper describes the implementation of a general and embedded decoder for the evaluation of unstructured low-density parity-check (LDPC) codes over additive-white Gaussian noise (AWGN) channels. The decoder, which has a serial architecture and moderate throughput, is a peripheral connected to the embedded Power PC processor of a Xilinx Virtex-II Pro FPGA and is managed by the processor. This method of hardware/software implementation provides the maximum flexibility for the development and rapid prototyping of the hardware-based simulator system. The decoding algorithm proposed in this paper belongs to the class of min-sum with correction factor in which the correction factor updates with the log-likelihood ratio (LLR) values.
Keywords :
AWGN channels; decoding; field programmable gate arrays; parity check codes; AWGN channels; LDPC codes; LDPC decoder; Xilinx Virtex-II Pro FPGA; additive-white Gaussian noise channels; embedded PowerPC processor; hardware-based simulator system; hardware-software implementation; log-likelihood ratio values; reconfigurable FPGA implementation; unstructured low-density parity-check codes; AWGN; Computer architecture; Decoding; Energy management; Field programmable gate arrays; Gaussian noise; Hardware; Parity check codes; Power system management; Throughput;
Conference_Titel :
Signals, Circuits and Systems, 2008. SCS 2008. 2nd International Conference on
Conference_Location :
Monastir
Print_ISBN :
978-1-4244-2627-0
Electronic_ISBN :
978-1-4244-2628-7
DOI :
10.1109/ICSCS.2008.4746952