A Q- and bandwidth-enhancing design technique for active inductors using parasitic cancellation

This paper presents the design technique and detailed equations of a high frequency, high-Q, active inductor (AI) that can be designed for frequencies above 6 GHz using non-minimal-length CMOS technologies, e.g. 130 nm CMOS, and used for industry because of the bias controls available in the topology. The design is achieved via a parasitic cancellation technique. An inductance of 2.89 nH is achieved at 6.5 GHz with a Q of 69. The designed active inductor is then used to obtain high-gain, narrowband tuning and an output matching element at or above 6.5 GHz using this technology. Although this AI design is used single-endedly in this work, it can be used differentially as well since the design is fully bi-directional. The inductor less LNA parameters at 6.5 GHz: S21 of 18 dB, NFmin of 3.22 dB, NF of 6 dB and S22 less than -15 dB with only 6.4 mW (plus 2.5 mW for narrow-band output match) power consumption for 1.2 V supply.