Title :
Does the floorplan of a chip affect its yield?
Author :
Koren, Zahava ; Koren, Israel
Author_Institution :
Massachusetts Univ., Amherst, MA, USA
Abstract :
The floorplan of a VLSI chip and its projected yield are usually considered to be completely unrelated issues. This commonly used assumption does not necessarily hold for several recently designed VLSI chips that incorporate some defect tolerance. The purpose of this work is to investigate the relationship between floorplanning and yield for this type of chip
Keywords :
VLSI; SLSI chip; VLSI chip; alpha chip; defect tolerance; floorplan; projected yield; yield analysis; Circuit faults; Contracts; Industrial engineering; Integrated circuit modeling; Integrated circuit yield; Large scale integration; Operations research; Redundancy; System testing; Very large scale integration;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 1993., The IEEE International Workshop on
Conference_Location :
Venice
Print_ISBN :
0-8186-3502-9
DOI :
10.1109/DFTVS.1993.595754
