DocumentCode
2343011
Title
On improving a fault simulation based test generator for synchronous sequential circuits
Author
Guo, Ruifeng ; Reddy, Sudhakar M. ; Pomeranz, Irith
Author_Institution
RA1-329, Intel Corp., Hillsboro, OR, USA
fYear
2001
fDate
2001
Firstpage
82
Lastpage
87
Abstract
We propose several techniques to improve a simulation based test pattern generation procedure for sequential circuits. The effectiveness of the proposed techniques is demonstrated through experimental results on a large set of benchmark circuits
Keywords
automatic test pattern generation; fault simulation; integrated circuit testing; integrated logic circuits; logic testing; sequential circuits; PROPTEST; fault simulation based test generator; flip-flop values; simulation-based ATPG; state driven circuit initialization; synchronous sequential circuits; test pattern generation procedure; Circuit faults; Circuit simulation; Circuit testing; Compaction; Computational modeling; Fault detection; Sequential analysis; Sequential circuits; Synchronous generators; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 2001. Proceedings. 10th Asian
Conference_Location
Kyoto
ISSN
1081-7735
Print_ISBN
0-7695-1378-6
Type
conf
DOI
10.1109/ATS.2001.990264
Filename
990264
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