Hierarchical fault simulation in combinational circuits

A method is presented for speeding up fault simulation in combinational circuits by taking advantage of a hierarchical circuit description. The parallel-pattern single-fault-propagation technique is combined with the concept of fanout-free regions, and this approach is then extended to exploit hierarchy. A number of illustrative experiments demonstrate the efficiency of the proposed method and substantiate the gains in simulation speed. Besides the savings in CPU time, the method results in a significant reduction in the memory requirements for creating and maintaining the computational model of the circuit to be simulated