Hierarchical testability measurement and design for test selection by cost prediction

Problems associated with test costs for complex electronic systems are discussed and a test strategy planner (TSP) is proposed which uses cost prediction throughout each design stage of a product to analyze the test costs and suggest methods of reducing the total product cost by design for test (DFT) choices. The TSP described is aimed at DFT applied to large integrated circuits designed within a standard-cell-based design system. However, the approach can be expanded both to encompass full-custom design of chips and to take in factors that affect board/system level implications of DFT at chip level